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4.2.9 Memory architecture

The WRAPPER machine model is aimed to target efficiently systems with highly pipelined memory architectures and systems with deep memory hierarchies that favor memory reuse. This is achieved by supporting a flexible tiling strategy as shown in figure 4.8. Within a CPU computations are carried out sequentially on each tile in turn. By reshaping tiles according to the target platform it is possible to automatically tune code to improve memory performance. On a vector machine a given domain might be sub-divided into a few long, thin regions. On a commodity microprocessor based system, however, the same region could be simulated use many more smaller sub-domains.

Figure 4.8: The tiling strategy that the WRAPPER supports allows tiles to be shaped to suit the underlying system memory architecture. Compact tiles that lead to greater memory reuse can be used on cache based systems (upper half of figure) with deep memory hierarchies, long tiles with large inner loops can be used to exploit vector systems having highly pipelined memory systems.
\resizebox{5in}{!}{
\includegraphics{s_software/figs/tiling_detail.eps}
}


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Next: 4.2.10 Summary Up: 4.2 WRAPPER Previous: 4.2.8 Communication primitives   Contents
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