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Next: 4.2.2 Supporting hardware neutrality
Up: 4.2 WRAPPER
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Contents
4.2.1 Target hardware
The WRAPPER is designed to target as broad as possible a range of
computer systems. The original development of the WRAPPER took place
on a multi-processor, CRAY Y-MP system. On that system, numerical code
performance and scaling under the WRAPPER was in excess of that of an
implementation that was tightly bound to the CRAY systems proprietary
multi-tasking and micro-tasking approach. Later developments have been
carried out on uniprocessor and multi-processor Sun systems with both
uniform memory access (UMA) and non-uniform memory access (NUMA)
designs. Significant work has also been undertaken on x86 cluster
systems, Alpha processor based clustered SMP systems, and on
cache-coherent NUMA (CC-NUMA) systems such as Silicon Graphics Altix
systems. The MITgcm code, operating within the WRAPPER, is also
routinely used on large scale MPP systems (for example, Cray T3E and
IBM SP systems). In all cases numerical code, operating within the
WRAPPER, performs and scales very competitively with equivalent
numerical code that has been modified to contain native optimizations
for a particular system Hoe et al. [1999].
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Copyright © 2006
Massachusetts Institute of Technology |
Last update 2018-01-23 |
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